1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device including an alignment mark used in a photolithography process.
This application is counterpart of Japanese patent application, Serial Number 318501/2003, filed Sep. 10, 2003, the subject matter of which is incorporated herein by reference.
2. Description of the Related Art
Conventionally, a metal oxide ferrodielectric substance (hereinafter referred to as a ferrodielectric substance) and a metal oxide paradielectric substance (hereinafter referred to as a high-dielectric substance; in this specification, a paradielectric material having a dielectric constant of about 10 or more is referred to as a high-dielectric substance) are used for a semiconductor device. A semiconductor device using the ferrodielectric substance will be mainly described in the following.
In the semiconductor device using the ferrodielectric substance, a semiconductor device using a Bi (bismuth) layer-shaped compound of SrBi2Ta2O9 (hereinafter, a substance having a varied composition of this substance and a series of additive represented by Nb (niobium) to or for this substance are referred to as SBT) or lead zirconate titanate Pb(Zr1-xTix)O3 (hereinafter, a substance having a varied composition of this substance and a series of groups of compounds produced by adding an additive represented by La (lanthanum) or Ca (calcium) to this substance are referred to as PZT) has been brought into practical use. Then, ferrodielectric substances in the studying stage include such a substance referred to as BLT that is produced by adding La (lanthanum) to bismuth titanate and a solid solution of the ferrodielectric substance described above and the other dielectric substance. In any cases, there is such a common thing that the substances need to be subjected to a heat treatment in an oxygen atmosphere so as to show a ferrodielectric property as an oxide crystal and the invention can produce an equivalent effect. Thus, a case where a ferrodielectric film, in particular, an SBT film is used will be described in the following description.
All of the ferrodielectric substances including the SBT are metal oxide crystals and need to be subjected to a heat treatment at as high a temperature as from 600° C. to 800° C. so as to recover process damage caused at the time of crystallizing these substances and sputtering or etching the substances in the later processes. In addition, in many cases, this heat treatment is performed in an oxygen atmosphere. For this reason, in a case where a semiconductor device manufactured before forming a ferrodielectric capacitor has a wiring and a contact construction formed of W, the wiring and the contact construction are easily oxidized in the oxygen atmosphere to lose conductivity. Thus, it is necessary to take some countermeasure to prevent the oxidation of them.
On the other hand, the semiconductor device including the above-mentioned dielectric substances is manufactured by a photolithography process. Then, in this process, it is necessary to overlay (align) a pattern to be formed hereafter on (with) a pattern formed on an underlying layer with high accuracy. Thus, in addition to a device pattern, a pattern for constructing an alignment mark that only aims to perform the alignment with high accuracy are also formed at the same time. The alignment mark is broadly divided into three kinds of marks of a mark for rough alignment (search mark) and a mark for fine alignment (fine mark) both of which when a resist (photosensitive agent) is exposed to light by the use of a pattern exposure system, are read by the pattern exposure system and a mark for alignment and measurement that is used for detecting the amount of deviation from alignment by the use of an alignment measurement instrument after the resist is exposed to light and developed. These alignment marks are not directly related to the function of the semiconductor device but are necessary and indispensable at the time of manufacturing the semiconductor device.
There are three main alignment marks, as described above, and problems of the respective alignment marks and measures to solve the problems are the same for the three alignment marks. Thus, the mark for alignment and measurement will be described in the following. FIGS. 5A and 5B are schematic views of a typical structure of the mark for alignment and measurement of a conventional semiconductor device. FIG. 5A shows a schematic plan view of the mark for alignment and measurements, and FIG. 5B shows a cross sectional view taken on a line 5B—5B in FIG. 5A, the mark for alignment and measurement is formed of two patterns of an OUT-BOX 900 and an IN-BOX 910. The pattern shape of the OUT-BOX 900 is formed in a rectangular outside shape having a specified width and the pattern shape of the IN-BOX 910 is formed in a rectangular shape. The IN-BOX 910 is arranged inside the OUT-BOX 900.
For example, let's think a case where a second pattern layer yet to be formed is aligned with a first pattern layer of an underlying layer. First, the OUT-BOX 900 is formed of the first pattern layer and then the IN-BOX 910 is formed in a lithography process of the second pattern layer. Here, for example, let's assume that the IN-BOX 910 of the second pattern layer is formed of a resist. By measuring the marks for alignment and measurement constructed of the OUT-BOX 900 and the IN-BOX 910 by means of an alignment measurement instrument, the amount of deviation from alignment of the first pattern layer relative to the second pattern layer is detected. In a case where the amount of deviation from alignment is larger than a specified value, the resist is totally removed and another second pattern layer is again formed by the use of the obtained alignment correction value. Here, conversely, in a case where the IN-BOX 910 is formed of the first pattern layer, the OUT-BOX 900 is formed of the second pattern layer and then the amount of deviation from alignment is detected in the same way. In both cases, the same following operations will be performed.
FIG. 5A is a drawing corresponding to a case where the first pattern layer is a layer in which a contact hole is formed and where the OUT-BOX is simultaneously formed at the time of etching the contact hole and where the IN-BOX is formed in the following process. The structure shown in FIG. 5B is manufactured by the method to be described below. First, a contact hole is formed in an interlayer insulation film 901 in a contact hole etching process. Then, a barrier metal is formed of, for example, Ti/TiN (titan/titan nitride). Then, a tungsten film (hereinafter referred to as “W film”) is formed by a tungsten chemical vapor deposition method (hereinafter referred to as “W-CVD method”). In the barrier metal and the W film, a metal film 902 is formed only inside the contact hole by the use of an etch back method or a chemical mechanical polishing method (hereinafter referred to as “CMP method”). At this time, in a case where the etch back method is used, as shown in FIG. 5B, a metal layer remains in the shape of a side wall in a mark region and in a case where the CMP method is used, the metal layer remains in the more expanded region. Thereafter, an interlayer insulation film 903 is formed and the IN-BOX is formed of the second pattern layer. A silicon nitride film, for example, is used for the interlayer insulation film 903. Alternatively, in some case, the first pattern layer is formed and then a capacitor electrode is directly formed without forming the interlayer insulation film 903. In this case, the insulation film 903 shown in FIG. 5B becomes a capacitor electrode film.
Even if the stepped portions formed in the shape of side wall are covered with the silicon nitride film or the capacitor electrode film, as shown in FIG. 5B, W (tungsten) is heavily oxidized to deform the shape of the alignment mark, as shown in FIGS. 6A and 6B, by the heat treatment performed in the oxygen atmosphere at the time of forming the ferrodielectric substance. FIG. 6A shows an example of deformed shape of the IN-BOX and FIG. 6B shows an example of deformed shape of the OUT-BOX. Both of them are photographs taken with an optical microscope. When the alignment mark is deformed in the shape, a function as the alignment mark is not performed, and further very serious problems in manufacturing the semiconductor device such as the occurrence and separation of particles in the following processes are caused. Moreover, FIG. 7 shows a photograph of cross section of an alignment mark portion oxidized by a focused ion beam (hereinafter referred to as “FIB”) and shows a state where the W film is oxidized and expanded to break the upper layer film.
Among publicly known documents relating to the present invention is the patent document 1 described below. In the patent document 1 is described a technology of replacing an accessory pattern of a pattern other than a semiconductor integrated circuit by a set of a plural constituent patterns. [Patent Document 1] JP-A-2000-171966
In addition to the above-mentioned problems of oxidation and separation of the alignment mark portion, in the pattern shape of the OUT-BOX 900 shown in FIGS. 5A and 5B whose outside shape is rectangular, there is presented a problem that since the pattern widths of the corner portions become larger than the pattern widths of the sides portions, voids are apt to occur at the corner portions. The occurrence of voids results in increasing the amount of etch back or CMP when the W etch back or the W-CMP is performed in the later process and hence causes a reduction in uniformity in the plane of a wafer.